System Verilog Core Testbench Products

For those customers ready to make the leap to System Verilog from a prior verification language or just upgrade to a feature-rich directed random testbench, the System Verilog Core Testbench is the perfect vehicle.

The System Verilog Core Testbench includes the following elements that together comprise a complete directed random testbench for a networking application.

• Packet Generators and checkers for end-to-end packet checking.
• File I/O to read in test parameters to override constrained random variables.
• Microprocessor control interface for register accesses.
• Models of statistics counters.
• Interface wrappers to BFMs.
• A testbench hierarchy.
• Perl scripts and Makefiles.

A complete testbench is available, ready to be customized to the specific desired applicaiton. While some projects would benefit most from leveraging a few elements of the System Verilog Core Product, other projects can leverage it all. The testbench is partitioned to easily allow individual elements to be redeployed. Often base classes exist like the traffic generator base class and packet base class to aid the customization.